System on a Chip technology (SoC) is widely used in mobile devices such as cellular phones, media players, tablet PCs, etc. Each of such chip integrates hundreds of thousands to several millions elements, many of them are bi-stable components (i.e., flip flops) that are capable of retaining binary states.
During normal operation, such a chip consumes a significant amount of energy from the device battery, while a significant portion of this energy consumption results from the large number of flip flops. A continuous operation of the chip in a normal manner typically results in a very fast battery exhaustion. Typically, a mobile device is non active (for example in standby state) most of the time, and during this time most of the energy consumption is due to static power leakage. Furthermore, in today's deep sub-micron manufacturing processes, 45 nm and below, static power consumption has become even a more dominant factor, impeding further advancement of SoC designs.
Power gating (PG) is one of the common techniques for reducing power consumption resulting from static leakage in a system on chip for mobile devices. A high PG efficiency is obtained due to a complete disconnection of specific regions of the chip from the power supply during a standby state. However, a major drawback of using the PG technique is the complete loss of the circuit state which is intolerable. Therefore, in order to restore the state of the circuit back to its state prior to standby state, significant additional time and dynamic power is required. This drawback is unacceptable in many applications.
To overcome the above drawback of the PG technique, a State Retention Power Gating approach (SRPG) has been developed. According to this approach, the state of the design is retained during standby by using a low-leakage state-retention memory cell (so called SRPG cells) for each and every flip-flop (FF) in the power-gated regions. The SRPG cells remain powered during standby, consuming relatively low energy, and in such a manner the state retained by those cells enable restoration of the design state to its previous state (i.e. the state before power down).
The main disadvantage of retaining the entire flip flops data is the area increase due to the additional SRPG cells. Using SRPG technique to retain the entire flip flops data results in an increase of 5% to 10% in the area of the chip. This technique also significantly increases the complexity of the physical design. Moreover, the excessive number of SRPG cells also increases the static power consumption in standby state, relative to the PG implementation.
Sheets, (http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-70.pdf) (chapter 3 of the document), suggests that a subset of storage elements with insignificant values can be determined by analyzing their read and write patterns across a set of possible states (referred to as checkpoints in his work) when the system is stationary. If a storage element is never read again after a certain checkpoint, or it is rewritten before it is next read, its content can be safely discarded. Sheets further suggests classifying all the states into two groups: persistent state and temporary state for each checkpoint. Sheets presents a general framework to reduce the state maintenance requirements during sleep mode. The framework is applied to Finite State Machines and microprocessors. Partitioning the system into subsystems with individually power domains allows fine-grain control of the power for portions of the chip (sub designs).
Sheets' approach can't be easily applied to a large design, since it is not practical to fully represent a typical design, which is composed of several sub designs, by a single FSM. Moreover, the power management proposed by Sheets relates to power gating of a sub design rather than a single flip-flop. This leads to low granularity and less efficient power management (i.e. in case one of the flops in a sub design needs retention then the whole sub design flops and the related logic should be retained).
Bashari et al., in their paper “Selective State Retention Design Using Symbolic Simulation” (in Design, Automation & Test in Europe Conference & Exhibition, pp. 10054-10059, 20-24 Apr. 2009) suggest using a formal model checking technique called Symbolic Trajectory Evaluation (STE) to check the design behavior. However, this approach is case specific since a fundamental requirement to this approach is the construction of sets of properties for each functional unit in question. Moreover, this approach performs analysis at the unit level, and not at the flip flop level, and no quantification for the retention flip flops reduction is presented.
It is therefore an object of the present invention to overcome said significant static power consumption obstacle, which impends the development of mobile devices that are based on CMOS 45 nm or below technology.
It is another object of the present invention to provide a state retention in a system on chip which provides a significant saving of power consumption (i.e., battery energy) compared to the existing SRPG approach.
It is still another object of the present invention to provide a significant saving of area in a system on chip compared to the SRPG approach.
It is still another object of the invention to enable a full recovery of the system on chip upon power resumption following a standby state.
It is still another object of the invention to provide a method for saving area and power in a system on chip, which is entirely independent of the software which will eventually run on the chip.
It is still another object of the invention to provide said method which is generic, and is independent of the VLSI specific design.
It is still another object of the invention to provide a method for significantly reducing the physical design (backend) implementation complexity when applying state retention.
It is still an object of the present invention to provide all said advantages in an efficient and low cost manner, which is performed during the design stage.
Other objects and advantages of the invention will become apparent as the description proceeds.